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motorola semiconductor technical data this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 2003 33397 simplified application diagram document order number: MC33397/d rev 2.0, 03/2003 33397 advance information dual/hex low-side switch dual/hex low-side switch with both spi and parallel input control the 33397 is a low-side switch that is user configurable to be either two 333 m ? outputs (dual mode) or six 900 m ? outputs (hex mode). each output is internally current limited and short-ci rcuit protected. outp ut fault detection capability includes ?off state? open loads and ?on state? short-to-battery conditions. faults for each output are latc hed into the fault register and serially shifted out during serial communication. features ? user configurable to be either two 333 m ? outputs (dual mode) or six 900 m ? outputs (hex mode) ? output inductive energy clamps ? parallel input (3.3 v and 5.0 v compatib le) or serial peripheral interface (spi) control ? 8-bit spi control and fault diagnostics ? short-to-battery detection and shutdown with automatic retry ? off-state open-circuit detection ? programmable overvoltage shutdown (v pwr pin) ? undervoltage shutdown (v dd pin) ? sleep mode?i dd 25 a (1.0 a typical) dw suffix plastic package case 751e 24-lead soicw ordering information device temperature range (t a ) package MC33397dw/r2 -40 to 125c 24 soicw micro- controller with bus cmos input logic cmos serial shift registers and latches output switches and sense circuits +v bat 5-8, 17-20 gnd 1 2 11 12 14 23 a5 a4 a3 a2 a1 a0 v pwr 24 v dd 13 en en cs sclk si so 15 10 3 4 9 33397 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 2 figure 1. 33397 simplified block diagram + - + - + - - + - + - + - + - + + - 8-bit spi interface logic logic logic logic logic logic parallel gate control and mode control logic i limit i limit i limit i limit 10 s filter overvoltage shutdown low v dd detect and por timer s r q 0.75 v dd 0.25 v dd v pwr 1.2 ? 1.2 ? 50 v 50 v 50 v 50 v 50 v 50 v 40 a 40 a 40 a 40 a 40 a 40 a 3.0 v 3.0 v 3.0 v 3.0 v 3.0 v 3.0 v sleep mode sleep mode sleep mode sleep mode sleep mode sleep mode dual mode dual mode dual mode dual mode cs si so sclk 10 a 10 a 10 a 30 v 3.0 v v dd 1.2 ? 1.2 ? 1.2 ? 1.2 ? v dd p1 en a3 a2 a1 i limit i limit p2 p0 a5 a4 a0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 3 pin function description pin pin name description 1, 2, 11, 12, 14, 23 a0?a5 power outputs 3 sclk spi clock input 4 si spi serial input 5?8, 17?20 gnd power and signal ground 9 so spi serial output 10 cs spi chip select 13 v dd supply input pin 15 en enable 16 p0 in hex mode, p0 controls output a0. in dual m ode, p0 controls outputs a0, a4, and a5 simultaneously 21 p1 in hex mode, p1 controls output a1. in dual m ode, p2 controls outputs a1, a2, and a3 simultaneously 22 p2 in hex mode, p2 controls output a2. p2 is also the mode control pin. if 0.25*v dd 33397 motorola analog integrated circuit device data 4 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit power supply voltage v pwr 50 v logic supply voltage v dd -0.3 to 7.0 v input pin voltage v in -0.3 to v dd +0.3 v esd voltage human body model (note 1) machine model (note 2) v esd1 v esd2 2000 200 v single pulse output clamp energy i o =500 ma, t j =150 c (hex mode) i o =1.5 a, t j =150 c (dual mode) j clamp1 j clamp1 50 100 mj recommended spi operating frequency f op 3.5 mhz storage temperature t stg -55 to 150 c operating junction temperature t j -40 to 150 c soldering temperature (for 10 seconds) t solder 260 c thermal resistance, junction-to-lead (note 3) r j-l 15 c/w notes 1. esd1 performed in accordance with the human body model (c za p =100 pf, r zap =1500 ? ) . 2. esd2 performed in accordance with the machine model (c zap =200 pf, r zap =0 ? ). 3. leads 5, 6, 7, 8, 17, 18, 19, and 20 are soldered to a heat-sinking ground plane. see figure 14. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 5 static electrical characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, -40 c t a 125 c, unless otherwise noted. characteristic symbol min typ max unit power input v pwr supply current (all outputs on) i pwr(on ) ?1.050 a v pwr sleep state supply current v pwr =17 v, spi bit 7=1, en =5.0 v i pwr(ss) ?1.010 a overvoltage shutdown v p(ov) 30 33 38 v overvoltage shutdown hysteresis v p(ov)hys 0.3 0.5 1.5 v logic supply current (all outputs on) i dd ? 1.20 5.0 ma logic supply current (sleep state: en =5.0 v, spi bit 7=1) i ddss ?1.025 a logic supply undervoltage inhibit threshold v dd(lvi) 2.5 3.0 3.5 v input input voltage (p0, p1, p2, en , si, sclk, cs ) high low v ih v il 0.8 ? ? ? ? 0.2 v dd dual mode threshold (p2) upper threshold lower threshold v dmh v dml 0.7 0.2 0.75 0.25 0.8 0.3 v dd input current pull-down (p0, p1)-v in =v dd pull-down (p2)-v in =v dd pull-up (cs )-v in =0 v pull-up ( en )-v in =0 v pull-up (sclk, si)-v in =2.5 v i inpd i inpd i inpu i inpu i inpu 10 5.0 -20 -100 -10 20 10 -10 ? 0 30 30 -5.0 -10 10 a output output drain to source on resistance (hex mode) (note 4) i o =0.35 a, t j =-40 c i o =0.35 a, t j =25 c i o =0.35 a, t j =150 c r ds(on) 0.39 0.51 0.51 0.5 0.7 1.0 1.2 1.2 1.2 ? output voltage clamp i ds =20 ma, output off i ds =200 ma, output off bv dss 50 50 55 56 60 60 v output leakage current (hex mode) en =h, bit7=1, v drain =24 v i o(ss) 0?10 a output logic voltage (so), i load =1.0 ma high low v oh v ol 0.8 ? ? ? ? 0.2 v dd output tristate leakage (so), v so =2.5 v i sot -10 ? 10 a notes 4. this parameter is specified for hex mode. in dual mode, the parameter will be three times smaller. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 6 fault detection output self-limiting current (hex mode) (note 5) outputs programmed on i o(lim) 1.0 1.5 2.0 a output fault detect threshold voltage outputs programmed off, en =0 v of(th) 0.5 0.6 0.7 v dd output off open load detect current output programmed off, en =0 i o(off) 20 40 80 a notes 5. this parameter is specified for hex mode. in dual mode, the parameter will be three times smaller. static electrical charac teristics (continued) characteristics noted under conditions 4.75 v v dd 5.25 v, -40 c t a 125 c, unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 7 dynamic electrical characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, -40 c t a 125 c, unless otherwise noted. characteristic symbol min typ max unit output timing output rise time v pwr =14 v, r load =25 ? , 20?80% t r 1.0 1.2 10 s output fall time v pwr =14 v, r load =25 ? , 80?20% t f 1.0 2.0 10 s output turn-on propagation delay t pon 1.0 4.0 10 s output turn-off propagation delay t poff 1.0 4.0 10 s fault timing output short-to-battery fault filter time t ss 30 50 90 s output refresh timer t ref 3.0 4.1 6.0 ms output refresh timer duty cycle d 0.2 1.56 3.0 % output off-state open circuit fault filter time t oof 30 50 90 s spi/miscellaneous timing so disable time (10 k pull-up resistor on so) cs =0.8 v to so > 0.8*v dd t sodis ? 80 110 ns so enable time (10 k pull-up resistor on so) cs =0.8 v to so low impedance t soen ? 80 110 ns so rise time cl < 200 pf t sorise ?3050 ns so fall time cl < 200 pf t sofall ?3050 ns so valid time falling edge of sclk to so valid t valid ?6580 ns required time between falling edge of cs to rising edge of sclk t lead ? 100 140 ns required time between rising edge of cs to falling edge of sclk t lag ?050 ns required time between si to rising edge of sclk t su ?2545ns por/ en wake-up timer t por 20 40 60 s mode change timer (p2) t mode 5.0 10 25 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 8 timing diagrams figure 2. spi timing diagram figure 3. operation waveforms for hex control cs t soen t valid t sodis t su t lag t lead sclk si so a3-a5 t fall cs t rise t pon t poff si sclk so po p1 p2 en a0 a1 a2 hiz note: in hex mode, the outputs are controlled by the spi or by the parallel inputs. however, p0, p1, and p2 only control a0, a1, and a2, respectively. when en goes high, the part is disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 9 figure 4. response times figure 5. short-to-battery fault v dd 0.2 v dd 0.8 v dd v ds 80% 20% p0, p1 0v 0v t f t r t poff t pon v in (p0, p1) v dd short-to-battery period v ds i limit i load i load t ref t ref t ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 10 figure 6. power on reset and mode select v dd t por v ddlv1 p2 a2 power on reset (internal signal) 2.5 v t mode t mode dual mode hex mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 11 figure 7. output on resistance versus temperature figure 8. drain to source clamp versus temperature figure 9. current limit versus temperature figure 10. i vpwr versus temperature figure 11. i dd versus temperature figure 12. i dd sleep state versus temperature -50 125 100 75 50 25 0 -25 0 1 0.8 0.6 0.4 0.2 1.2 t a , ambient temperature (deg c) r ds(on) ( ? ) 150 -50 125 100 75 50 25 0 -25 56.2 57.8 57.6 57.4 57.2 57 56.8 56.6 56.4 58 150 drain to clamp (v) t a , ambient temperature (deg c) 150 -50 125 100 75 50 25 0 -25 1.58 1.74 1.72 1.7 1.68 1.66 1.64 1.62 1.6 current (a) t a , ambient temperature (deg c) 0.2 0.16 0.12 0.1 0.08 0.06 0.04 0.02 0.14 0.18 current (a) t a , ambient temperature (deg c) 150 -50 125 100 75 50 25 0 -25 t a , ambient temperature (deg c) 150 -50 125 100 75 50 25 0 -25 1.4 1.3 1.2 1.1 1 0.9 5v supply current (a) 0.8 0 3 2.5 2 1.5 1 0.5 current (a) 150 -50 125 100 75 50 25 0 -25 t a , ambient temperature (deg c) typical characteristics f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 12 figure 13. spi input/output word definition table 1. truth table inputs en spi bit7 outputs comments p0 p1 p2 a0 a1 a2 a3 a4 a5 0 0 0 0 x off off off * * * hex mode * = outputs a3, a4, and a5 are spi controlled only. x = don't care. outputs a0, a1, and a2 are controlled either via spi or inputs p0, p1, and p2. 0 0 1 0 x off off on * * * 0 1 0 0 x off on off * * * 0 1 1 0 x off on on * * * 1 0 0 0 x on off off * * * 1 0 1 0 x on off on * * * 1 1 0 0 x on on off * * * 1 1 1 0 x on on on * * * 0 0 0 1 0 off off off off off off hex mode outputs a3, a4, and a5 are always off. outputs are not controlled via spi. outputs a0, a1, and a2 are only controlled via inputs p0, p1, and p2. sleep mode disabled. 0 0 1 1 0 off off on off off off 0 1 0 1 0 off on off off off off 0 1 1 1 0 off on on off off off 1 0 0 1 0 on off off off off off 1 0 1 1 0 on off on off off off 1 1 0 1 0 on on off off off off 1 1 1 1 0 on on on off off off 0 0 2.5 v 0 x off off off off off off dual mode outputs are also controlled via spi. spi fully functional. 0 1 2.5 v 0 x off on on on off off 1 0 2.5 v 0 x on off off off on on 1 1 2.5 v 0 x on on on on on on 0 0 2.5 v 1 0 off off off off off off dual mode outputs are not controlled via spi. outputs are controlled via inputs p0 and p1. sleep mode disabled. 0 1 2.5 v 1 0 off on on on off off 1 0 2.5 v 1 0 on off off off on on 1 1 2.5 v 1 0 on on on on on on x x x 1 1 off off off off off off all outputs disabled. spi is reset and ignored. no fault detection. msb 76543210 76543210 enable sleep mode the device will power up with sleep mode enabled. spi input word definition <-din motorola analog integrated circuit device data 33397 13 figure 14. approximate thermal resistance using pcb heat sinking 01 2 3 45 65 60 55 50 45 total square inches of heat sink flag area (flag 1 + flag 2) c/w 678 910 pcb heat sink flag 1 pcb heat sink flag 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 14 system/application information introduction the 33397 is a versatile dual-m ode low-side switch that can be output-configured as two 333 m ? open drain outputs in the dual mode or as six 900 m ? open drain outputs in the hex mode (r ds(on) @ 25c). each open drain output has internal current limit and short- circuit protection. current limit is typically 1.5 a, with 2.0 a maximum. the outputs can be input controlled via parallel inputs or the spi. three inputs provide parallel control, while a serial 8-bit word provides spi cont rol of the outputs. output fault detection capability includes of f-state open loads and on- state short-to-battery conditions. individual output faults are latched into the fault register and serially shifted out during serial communication to the 33397. the 33397 has both overvoltage and undervoltage shutdown. a low quiescent current sleep sl ate feature can be enabled or disabled on command via the spi port. functional pin description v dd logic power supply pin. a0?a5 a0?a5 are the drains of the 1.2 ? (max.) mosfets. they each have an internal voltage clamp of 50 v (min.) to clamp inductive loads during turn-off. when enabled, they are each internally current limited to a maximum of 2.0 a. if any output is in current limit (output voltage >3.0 v) for a time greater than t ss , the output will be disabled for a time t ref and then try to turn on again. when disabled, open circuits are detected if the output is less than 3.0 v for a time of t ss . either type of fault is reported as a fault on the spi output word. if en input is high and spi bit 7=1, the pull-down current sources on the outputs are disabled to minimize v dd supply current. in hex mode, all six outputs are independent. outputs a0, a1, and a2 are controlled by either the spi input word bits 0, 1, and 2, respectively, or parallel inputs p0, p1, and p2. outputs a3, a4, and a5 are controlled only by spi input word bits 3, 4, and 5, respectively. in dual mode, outputs a0, a4, and a5 are all controlled simultaneously by input p0 or by spi bits 0, 4, and 5. all three bits must be high to enable this output via the spi. outputs a1, a2, and a3 are all controlled simultaneously by input p1 or by spi bits 1, 2, and 3. all three bits must be high to enable this output via the spi. p0?p2 in hex mode, p0 is the parallel input to control output a0. it is or'd with spi bit 0 to enable output a0. either one will enable output a0. in dual mode, p0 co ntrols outputs a0, a4, and a5 simultaneously. p0 has a pull down current of 10 a. it is ignored when en is high and bit 7=1. in hex mode, p1 is the parallel input to control output a1. it is or'd with spi bit 1 to enable output a1. either one will enable output a1. in dual mode, p1 co ntrols outputs a1, a2, and a3 simultaneously. p1 has a pull-down current of 10 a. it is ignored when en is high and bit 7=1. in hex mode, p2 is the parallel input to control output a2. it is or'd with spi bit 2 to enable output a2. either one will enable output a2. p2 also is used to program the 33397 to either a dual or hex output device. the 33397 will be the hex mode if p2 is biased above 0.75*v dd (typical) or below 0.25*v dd (typical). normal 5.0 v control logic on this parallel input will maintain the 33397 in hex mode and allow control of output a2. if 0.25*v dd motorola analog integrated circuit device data 33397 15 cs cs is the chip select to enab le the spi interface. when cs is high, no spi communication is possible. when cs goes low, si will be read on each rising sclk edge and so will shift on each sclk falling edge. when cs goes high, the bits present in the spi input register will be interpreted as the spi input command. also when cs goes high, all faults that were latched into the spi output register are cleared. if faul ts are still present on outputs, they will be re-latched after t ss . en en must be low for complete ic functionality in either the dual or hex mode. when en transitions low while in the sleep mode or when the ic is powered up from v dd , a power-up timer of 40 s is started to allow the 33 397 to determine which mode it is in (hex or dual). during this time all parallel inputs and serial control spi bits will be ignored and all outputs will remain off. if en transitions low when not in the sleep mode, this ?dead? time will not occur. if a one was written to bit 7, the 33397 will be in the sleep mode when en goes high. in this mode all spi registers are reset to zero and all faults are cleared. no fault detection is possible. the standby supply current on v dd and v pwr is minimized. applications a voltage on the p2 input pin determines the mode. all six outputs can operate either independently (hex mode) (figure 15) or in paralleled groups of three (dual mode) (figure 16). in the dual mode, outputs a0, a1, and a2 are controlled by parallel inputs p0, p1, and p2, respectively, and they are also controlled by th e spi port with which they are or?d. on the other hand, outputs a3, a4, and a5 are controlled only through the spi port. when the voltage on p2 is between 0.25 v dd and 0.75 v dd (i.e., when p2 is held at an intermediate voltage, neither high nor low), the 33397 operates in the dual mode. however, the p2 pin must stay at that level for a minimum specified time. in this mode, outputs a0, a4, and a5 are all controlled in parallel by input p0. outputs a1, a2, and a3 are all controlled in parallel by input p1. both outputs can also be controlled via the spi port as well, but only if the three outputs are commanded on at the same time. figure 15. hex mode application circuit figure 16. dual mode application circuit 33397 a5 a4 sclk si gnd gnd gnd gnd so cs a3 a2 v pwr a0 p2 p1 gnd gnd gnd gnd p0 en a1 v dd v bat v bat v dd v dd (optional) parallel inputs from microprocessor to micro- processor v bat a5 a4 sclk si gnd gnd gnd gnd so cs a3 a2 v pwr a0 p2 p1 gnd gnd gnd gnd p0 en a1 v dd (optional) parallel inputs v bat 33397 v dd from microprocessor to micro- processor v bat v bat v bat v bat v bat v bat f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 16 package dimensions dw suffix (24-lead soic wide body) plastic package case 751e-04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. -a- -b- p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t -t- g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 17 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33397 motorola analog integrated circuit device data 18 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33397 19 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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